The present invention relates to a semiconductor memory device and a control method for the semiconductor memory device, and more particularly, it relates to improved serial-parallel and parallel-serial converting sections of a semiconductor memory device which includes a plurality of serial-access ports.
A semiconductor memory device including a plurality of serial-access ports is known in the prior art. FIG. 4 shows an example of such a semiconductor memory device, which has one input port and two output ports. This semiconductor memory device includes one write bus, two read buses A and B, line registers in which data obtained immediately after reset are stored, a memory cell array section including "0"th to (2n+1)th bit-line pairs, write registers the number of which is equal to that of the bit-line pairs, read A registers which correspond to the read bus A and the number of which is equal to that of the bit-line pairs, and read B registers which correspond to the read bus B and the number of which is equal to that of the bit-line pairs. A write operation in which data are written to the line registers and to the bit-line pairs of the memory cell array section is as follows: While serial data is being sequentially input to the write bus in synchronization with a clock, gates for selecting the line registers are first sequentially turned on, so that the "0"th to (2n+1)th data obtained immediately after reset are respectively written to the corresponding line registers, and then gates for selecting the write registers are sequentially turned on in synchronization with the clock, thereby allowing the data to be respectively written to the corresponding write registers. Thereafter, write data-transfer gates respectively connected to the write registers are simultaneously turned on, thereby transferring the data in the write registers into the corresponding bit-line pairs of the memory cell array section. Accordingly, the data are stored in parallel in the memory cell array section. When data are to be read out into the read bus A, the following read operation is carried out: First, gates for data-transfer A to the read A registers are simultaneously turned on, thereby transferring the parallel data from the bit-line pairs of the memory cell array section to the corresponding read A registers. At the same time, gates connecting the line registers to the read bus A are sequentially turned on in synchronization with the clock, thereby allowing the data in the line registers to be sequentially read out into the read bus A. Then, gates for selecting the read A registers are sequentially turned on in synchronization with the clock, thereby allowing the data in the read A registers to be serially read out into the read bus A. The operation of reading out data into the read bus B is carried out in the same manner as in the above-described operation of reading out data into the read bus A.
The conventional semiconductor memory device described above, however, has the following defect: As described above, the bit-line pairs in the memory cell array section are respectively connected to the read A registers corresponding to the read bus A, and also respectively connected to the read B registers corresponding to the read bus B. This requires the read A registers and the read B registers to be respectively aligned along two different lanes. Specifically, either the read A registers or the read B registers are required to be aligned along a lane located outside the lane along which the other registers (i.e., either the read B registers or the read A registers) are aligned. Therefore, the conventional semiconductor memory device is disadvantageous in that the memory chip thereof is large in size. Furthermore, the line registers are also required to be aligned along a lane located outside the lanes along which the read A registers and the read B registers are aligned, thereby causing the disadvantage of making the memory chip larger in size.
It is an object of the present invention to provide reduction in the chip size of a semiconductor memory device including a plurality of read buses (i.e., including a plurality of output ports), by reducing the number of read registers of the semiconductor memory device.